The present invention relates generally to the functional verification of electronic designs and more particularly to the partitioning of a design under verification for the integration of dynamic simulation and static timing analysis methodologies. Today's engineers are faced with an increasing difficult task of handling the verification of state-of-the-art system-on-chip (SoC) designs. The various verification techniques in use fall into two major categories, namely the dynamic event-driven simulation and the static timing analysis (STA) techniques. STA techniques are based on simplifying the general model of event-driven computation to that of a synchronous model. By taking advantage of the separation of the timing and functional behavior made possible by the synchronous design style, STA tools can apply complete, rigorous, and efficient algorithms that result in an overwhelming performance advantage when compared to event-driven simulation.
However, the STA techniques are not directly applicable to most designs at the full-chip level. This is because most designs are a combination of synchronous logic blocks and asynchronous logic blocks, or other non-synchronous design blocks, such as embedded analog blocks. One illustration of such a full-chip design 100 is shown in FIG. 1. This exemplary full-chip design consists of four clock domains: block 102 is driven by CLK1; block 104 is driven by CLK2; block 106 is driven by CLK3; and block 108 is driven by CLK4. In addition, the design also contains an asynchronous block 110 and an analog block 112. As shown in FIG. 1, a typical design at the full chip level violates the separation of timing and functionality implicit in the synchronous model. Although most of the modules might be synchronous, the clocking methodology that has four different clock domains can result in asynchronous interaction with each other. Furthermore, the design could contain non-synchronous design constructs 110 and 112 that cannot be verified by STA techniques.
As a result, both sets of solutions have their unique problems when applied to the verification of a complete design. On one hand, the static verification algorithms require strict adherence to the synchronous design style. On the other hand, the dynamic event-driven simulation is limited by the computing power and memory capacity of the computers used. Therefore, it would be advantageous to have an improved method for full chip level verification.
Disclosed is a full-chip level verification methodology that combines static timing analysis techniques with dynamic event-driven simulation. The specification discloses capabilities to partition a multiple-clock design into various clock domains and surrounding asynchronous regions automatically and to apply timing behavior during simulation on an instance by instance basis.
Static timing analysis techniques can be leveraged to verify the synchronous cores of each clock domain. The asynchronous regions of the design and the interaction between synchronous cores of the clock domains are validated using detailed dynamic event-driven simulation without the burden of carrying the interior timing attributes of the synchronous cores that have already been verified. With the unnecessary interior timing attributes of synchronous cores removed during dynamic simulation, the disclosed method accelerates the verification process and requires less computing power and memory capacities to complete the verification of the full chip.